Staff or Senior Staff Design Verification Engineer

Skills

About the Role

You will define and enhance verification methodologies for integrated digital, analog, and photonic devices. You will create test plans and scalable testbench components, execute block- and chip-level verification, develop validation flows, integrate analog IP, and complete coverage and design-verification signoff requirements.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, a related field, or equivalent experience
• At least 8 years of design verification and SystemVerilog experience
• At least 2 years of Python experience
• Expertise developing with the UVM library
• Experience with Xcelium, ModelSim, Questa, or VCS simulators
• Capacity to comply with federally mandated U.S. export control laws

Responsibilities

• Define and enhance design-verification methodologies for integrated digital, analog, and photonic devices
• Create and execute test plans for functional and performance goals
• Collaborate with architects and design engineers to define validation flows
• Create reusable and scalable testbench components
• Close coverage and complete design-verification signoff requirements
• Perform block-level and full-chip design verification
• Integrate analog design IP and develop simulation and emulation verification environments
• Create behavioral models and integrate models, test cases, and checkers into upper levels

Benefits

• Comprehensive medical, dental, and vision coverage
• Retirement savings matching program
• Life insurance, including basic, voluntary, and AD&D coverage
• Vacation, sick time, and public holidays
• Paid family leave
• Short-term and long-term disability coverage
• Commuter benefits
• Flexible hybrid workplace model
• Equity grants for eligible full-time employees