Signal Power Integrity Engineer On Off Chip
FuriosaAI is a South Korean AI semiconductor company building energy-efficient inference accelerators, servers, and software for enterprise and cloud AI deployments.
Funding history
Investors
About FuriosaAI
FuriosaAI develops the RNGD AI inference accelerator and NXT RNGD Server, alongside a software toolchain for compiling, optimizing, and deploying LLM and agentic-AI workloads.
Skills
Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
You will define signal- and power-integrity requirements from IP and system specifications. You will run electromagnetic, circuit, and system-level simulations and develop methodologies for advanced packaging. You will analyze and optimize on-chip, package, and PCB domains, guide design decisions, correlate measurements with simulations, and support lab debug and bring-up.
Requirements
- BS or MS in Electrical Engineering, Physics, or a related field
- 8+ years of component- and system-level signal- and power-integrity analysis experience
- Understanding of signal- and power-integrity fundamentals and methodologies
- Experience using VNA, TDR, and real-time oscilloscopes
- Proficiency with SIwave, HFSS, ADS, HSPICE, Allegro, RedHawk-SC, SC-ET, or RedHawk-3DIC
- Signal- and power-integrity analysis for high-speed digital systems and interfaces such as PCIe, DDR, and Ethernet
- Electromagnetic simulation of complex 3D structures
- On-chip backend sign-off for static and dynamic IR and EM
- On- and off-chip PDN modeling and budgeting
- On-chip glitch, jitter, DVD, cross-talk, TSV uncertainty, and multi-corner process-derating analysis
- Reference-clock jitter estimation and sign-off methodology development
- On-chip clock sign-off and process-variation analysis
Responsibilities
- Define signal- and power-integrity requirements from IP and system-level specifications
- Perform electromagnetic, circuit, and system-level signal- and power-integrity simulations
- Develop signal- and power-integrity methodologies for chiplet, 3D-IC, D2D, and C2C interfaces
- Analyze and optimize signal and power integrity across on-chip, package, and PCB domains
- Provide guidance on stack-up, interconnect routing, PDN architecture, decoupling, and component selection
- Collaborate to correlate measurements with simulations and improve system robustness
- Support lab debug and bring-up efforts
- Co-optimize signal- and power-integrity solutions with internal teams and partners