Senior Staff Physical Verification Engineer

Skills

About the Role

You will execute physical-verification checks from block through full-chip level and own the physical design flow from netlist to GDSII. You will perform signoff checks, manage verification runs, resolve layout integration issues, support tape-out milestones, and develop scripts and automation that improve physical-design methodology and efficiency.

Requirements

• Bachelor’s or master’s degree in electrical engineering, computer engineering, or a related field
• 5+ years of hands-on physical-verification experience with advanced TSMC process nodes
• Hands-on proficiency with Calibre
• Knowledge of the complete IC design flow from front-end design through back-end implementation and signoff
• Tape-out experience
• Python, Perl, Tcl, and Make scripting proficiency is a plus

Responsibilities

• Perform physical-verification signoff for advanced-node ASIC and SoC designs
• Run DRC, LVS, ERC, antenna, ESD, PERC, reliability, density, fill, and final tape-out checks using Calibre
• Monitor and manage hierarchical and flat physical-verification runs
• Optimize runtime and resource use, track results, prioritize issues, and drive closure toward tape-out milestones
• Resolve full-chip layout integration issues with Place and Route owners
• Support the physical design flow from netlist to GDSII
• Provide automation solutions for the tape-out flow
• Develop physical-design methodology, scripts, and flow automation using Perl and Tcl