Senior SoC Design Engineer
FuriosaAI is a South Korean AI semiconductor company building energy-efficient inference accelerators, servers, and software for enterprise and cloud AI deployments.
Funding history
Investors
About FuriosaAI
FuriosaAI develops the RNGD AI inference accelerator and NXT RNGD Server, alongside a software toolchain for compiling, optimizing, and deploying LLM and agentic-AI workloads.
Skills
Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
You will determine SoC architecture based on requirements, performance targets, and system specifications. You will document microarchitecture and design RTL. You will integrate subsystems, perform timing closure, lint checks, and synthesis, and support verification planning, physical implementation, silicon bring-up, and system-level verification.
Requirements
- Degree in Electronic Engineering, Computer Engineering, or a related field
- Bachelor's degree with 7+ years of RTL design experience or master's degree with 5+ years of RTL design experience
- SoC system IP design experience
- System- or chip-top-level design and integration experience
- Subsystem-top design experience
- Data-center or large-scale SoC design experience
- FPGA porting experience
- Understanding of AMBA bus protocols and bus interfaces
- Understanding of clock-domain crossing
- Design automation and scripting experience
- Experience using verification, synthesis, power-estimation, and EDA tools
Responsibilities
- Determine SoC architecture from requirements, performance targets, and system specifications
- Define microarchitecture documentation and design RTL
- Integrate subsystems and block tops
- Perform timing closure, lint checks, and synthesis
- Provide verification plans and collaborate to achieve coverage goals
- Identify physical implementation issues and incorporate them into RTL design
- Participate in silicon bring-up and system-level verification