Senior or Staff Mid-End Engineer for 3D Process Integration
Bitdeer is a technology company providing Bitcoin mining solutions.
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About Bitdeer
Bitdeer provides full-spectrum Bitcoin mining and high-performance computing solutions, including SEALMINER mining equipment, Minerbase cooling containers, cloud mining, co-mining, mining management applications, mining rights marketplaces, and large-scale data center operations. The company also offers AI cloud infrastructure with GPU computing, model training and deployment capabilities, and turnkey AI data center solutions for enterprise customers and developers. Bitdeer is headquartered in Singapore and operates globally.
Skills
About the Role
You will define wafer-on-wafer stacks and TSV and hybrid-bond interfaces, drive 3D-aware floorplanning and design rules, coordinate thermal and mechanical analysis, complete signoff, develop stacked-die test strategies, manage package and substrate handoffs, and track partner deliverables and integration risks.
Requirements
- BS, MS, or PhD in Electrical Engineering, Materials, Mechanical Engineering, or a related field
- At least 5 years of experience in 3DIC, advanced packaging, or process integration
- Experience taking at least one product through tapeout and assembly
- Hands-on experience with TSV and hybrid bonding
- Experience with wafer-on-wafer, chip-on-wafer, SoIC, CoWoS-class, or another 3D stacking flow
- Working knowledge of TSMC 3DFabric or an equivalent foundry 3D ecosystem, including design kits and rule decks
- Knowledge of thermal and thermal-mechanical behavior in stacked die
- Knowledge of SI/PI at die-to-die interfaces
- Ability to manage interfaces with foundries, memory IP partners, and OSATs
- Experience with DRAM-on-logic stacks, HBM-class integration, or high-bandwidth memory interfaces is preferred
- Experience with AI or HPC accelerators or other high-power high-bandwidth SoCs is preferred
- Familiarity with Ansys and Synopsys or Cadence 3D physical and signoff flows is preferred
- Exposure to stacked-die testing and yield debugging is preferred
- Experience establishing a 3D integration methodology is preferred
Responsibilities
- Own the wafer-on-wafer stack definition and TSV and hybrid-bond interface
- Co-define partitioning, bond-pad geometry, keep-outs, and alignment budgets with foundry and memory partners
- Drive bump, TSV, hybrid-bond, micro-bump, ballmap, and die-to-die floorplanning inputs
- Define and close DFM and 3D design rules
- Conduct design-rule and process-assumption reviews
- Coordinate thermal and thermal-mechanical analysis
- Apply analysis mitigations to floorplans, power delivery, and stack choices
- Drive thermal and SI/PI signoff across the die-to-die interface before tapeout
- Develop the 3D test strategy with DFT engineers
- Manage package and substrate co-design handoffs to the OSAT
- Address stackup, escape, assembly flow, yield, and reliability considerations
- Track foundry and memory-partner deliverables and milestones
- Identify integration risks and align the stack plan with the schedule