Senior Emulation Engineer
Velaura AI develops ultra-low-power silicon and software technologies for AI compute infrastructure. Its solutions serve hyperscale data centers and Physical AI applications such as robotics, autonomous systems, drones, and edge devices.
Maintainer signals as of 8/23/2026
Funding history
About Velaura AI, Inc.
Velaura AI is an AI compute infrastructure company developing ultra-low-power silicon and software technologies. Its Titan Core™ platform uses proprietary digital chip IP, low-voltage libraries, EDA flows, and design methodologies to improve performance per watt in AI accelerators while maintaining performance, yield, and reliability. The company also applies this technology to Physical AI systems, including industrial robots, autonomous machines, drones, humanoids, and edge devices. Velaura engages hyperscalers, XPU companies, and developers of next-generation AI infrastructure and Physical AI solutions.
Skills
Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
You will bring up, own, and scale emulation infrastructure for a next-generation Physical AI SoC. You will set up and optimize flows on Palladium, Veloce, and Zebu; resolve compile, elaboration, capacity, partitioning, and design-mapping issues; build regression automation and CI pipelines; support hardware-software co-verification and pre-silicon software bring-up; optimize debug and root-cause analysis; verify performance, latency, bandwidth, QoS, and real-time behavior; and collaborate across architecture, RTL, verification, software, and systems engineering.
Requirements
- 10+ years in hardware emulation and/or verification of complex digital systems.
- Hands-on experience setting up emulation flows on Palladium, Veloce, or Zebu.
- Ability to debug compile and elaboration issues on emulation platforms.
- Experience setting up and optimizing emulation regression flows.
- Strong analytical and problem-solving skills.
- Strong grasp of computer, microprocessor, and SoC architecture and digital design fundamentals.
- Understanding of CDC, clocking, and reset behavior in emulation bring-up.
- Experience with SystemVerilog, UVM, C, C++, transactors, and assertions.
- Understanding of memory systems, interconnects, caches, DMA engines, processors, or accelerators.
- Experience debugging complex system-level issues across hardware and software.
- Strong scripting and automation skills for build, regression, and CI pipelines.
- Ability to work effectively in a multidisciplinary team.
- Experience with design partitioning, capacity optimization, and multi-FPGA or multi-board emulation scaling.
- Experience with FPGA prototyping and pre-silicon software bring-up environments.
- Experience with hardware-software co-verification and system-level validation.
- Familiarity with low-power methodologies and their verification or emulation criteria.
- Experience with AI, machine learning, or edge AI hardware.
- Familiarity with robotics, drones, autonomous vehicles, or industrial automation systems.
- Experience verifying or emulating QoS, latency-sensitive, or real-time systems.
- Exposure to performance modeling, profiling, and workload characterization.
- Experience with ISO 26262, IEC 61508, IEC 61511, or ISO 13849.
- Experience using modern AI tools and workflows to accelerate engineering productivity.
Responsibilities
- Set up, own, and maintain emulation flows for the SoC on Palladium, Veloce, and/or Zebu.
- Bring up designs on the emulator and resolve compile, elaboration, capacity, partitioning, and design-mapping issues.
- Build and maintain regression flows while optimizing compile time, run time, throughput, and capacity utilization.
- Support hardware-software co-verification and pre-silicon software bring-up for firmware, drivers, runtime, and operating systems.
- Optimize on-emulator debug and drive fast hardware-software root-cause analysis.
- Verify performance, latency, bandwidth, QoS, and real-time behavior under representative workloads.
- Partner with architects, RTL engineers, and verification engineers on emulation strategy, transactor requirements, and coverage goals.
- Emulate compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and other SoC infrastructure.
- Build automation, scripting, and CI hooks for compile and regression pipelines.
- Contribute to FPGA prototyping, pre-silicon validation, and post-silicon debug.
- Apply AI-assisted verification and debug tools to improve productivity, quality, and coverage.
- Contribute to technical excellence and continuous improvement.
Benefits
- Equity participation
- Medical coverage
- Dental coverage
- Vision coverage
- Paid time off
- Flexible work arrangements
- Professional development opportunities