RTL Designer – Physical AI Compute
Velaura AI develops ultra-low-power silicon and software technologies for AI compute infrastructure. Its solutions serve hyperscale data centers and Physical AI applications such as robotics, autonomous systems, drones, and edge devices.
Maintainer signals as of 8/23/2026
Funding history
About Velaura AI, Inc.
Velaura AI is an AI compute infrastructure company developing ultra-low-power silicon and software technologies. Its Titan Core™ platform uses proprietary digital chip IP, low-voltage libraries, EDA flows, and design methodologies to improve performance per watt in AI accelerators while maintaining performance, yield, and reliability. The company also applies this technology to Physical AI systems, including industrial robots, autonomous machines, drones, humanoids, and edge devices. Velaura engages hyperscalers, XPU companies, and developers of next-generation AI infrastructure and Physical AI solutions.
Skills
Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
Design and optimize RTL for key portions of a Physical AI SoC, develop microarchitectures, define hardware interfaces and execution flows, contribute to compute and memory subsystems, optimize performance, power, and area, and collaborate through verification and physical design.
Requirements
- Experience designing RTL for complex digital systems
- Strong understanding of computer architecture, microarchitecture, and digital design fundamentals
- Experience with Verilog and SystemVerilog
- Familiarity with performance, power, and area tradeoffs
- Understanding of memory systems, interconnects, caches, DMA engines, or accelerator architectures
- Experience with hardware/software co-design and system-level performance optimization
- Strong debugging and problem-solving skills
Responsibilities
- Design, implement, and optimize RTL for key SoC components
- Develop robust and efficient microarchitectures
- Define hardware interfaces, execution flows, and memory hierarchies
- Contribute to compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and power-management logic
- Optimize designs for performance, power, area, scalability, and reliability
- Analyze performance bottlenecks and propose improvements
- Participate in design reviews
Benefits
- Performance-based incentives
- Equity participation
- Medical coverage
- Dental coverage
- Vision coverage
- Paid time off
- Flexible work arrangements