Principal Packaging Engineer
Velaura AI develops ultra-low-power silicon and software technologies for AI compute infrastructure. Its solutions serve hyperscale data centers and Physical AI applications such as robotics, autonomous systems, drones, and edge devices.
Maintainer signals as of 8/23/2026
Funding history
About Velaura AI, Inc.
Velaura AI is an AI compute infrastructure company developing ultra-low-power silicon and software technologies. Its Titan Core™ platform uses proprietary digital chip IP, low-voltage libraries, EDA flows, and design methodologies to improve performance per watt in AI accelerators while maintaining performance, yield, and reliability. The company also applies this technology to Physical AI systems, including industrial robots, autonomous machines, drones, humanoids, and edge devices. Velaura engages hyperscalers, XPU companies, and developers of next-generation AI infrastructure and Physical AI solutions.
Skills
About the Role
Own package architecture and development for next-generation SoCs, co-optimizing package, die, board, and system designs while leading packaging technologies, assembly interactions, signal and power integrity, thermal, mechanical, reliability, manufacturing, foundry, and test requirements.
Requirements
- Deep experience developing advanced semiconductor packages for high-performance SoCs.
- Strong understanding of package architecture, substrate technologies, bumping, assembly flows, and manufacturing.
- Experience co-optimizing package design with silicon, board, signal integrity, power integrity, thermal, and mechanical teams.
- Hands-on experience with signal integrity, power integrity, thermal, and reliability considerations in advanced packages.
- Ability to balance technical excellence with cost, yield, manufacturability, and schedule.
- Excellent communication skills and a collaborative, first-principles engineering mindset.
- Experience with chiplets, 2.5D integration, silicon bridges, or heterogeneous integration.
- Experience with HBM integration and high-bandwidth memory package architecture.
- Experience with advanced process nodes.
- Experience working with foundries, OSATs, and substrate vendors.
- Experience in an early-stage semiconductor company.
Responsibilities
- Own package architecture from concept through production for Velaura SoCs.
- Co-optimize package, die, board, and system design for performance, power, cost, and manufacturability.
- Drive package technology selection, including flip-chip, advanced substrates, fan-out, and future multi-die integration approaches.
- Lead package design, bump planning, substrate definition, escape routing, and assembly interactions with OSAT and substrate vendors.
- Own package-level signal integrity and power integrity planning for high-speed interfaces.
- Collaborate on thermal architecture, mechanical integration, reliability, DFM, and qualification.
- Work with foundry, assembly, substrate, and test partners to deliver products to production.
- Help define Velaura's long-term packaging roadmap.
Benefits
- Performance-based incentives
- Equity participation
- Medical coverage
- Dental coverage
- Vision coverage
- Paid time off
- Flexible work arrangements
- Professional development opportunities