Physical Design Engineer
Velaura AI develops ultra-low-power compute technology for cloud, edge, and physical AI applications. It also offers Teraflux Bitcoin mining hardware, fleet-management software, and related support for mining operators.
Maintainer signals as of 8/14/2026
Funding history
About Velaura AI
Velaura AI is a semiconductor and technology company that provides patented ultra-low-power silicon design technology, IP, toolflows, and custom chiplet solutions for AI compute platforms. Its customers include hyperscaler and XPU companies seeking reduced power consumption and higher compute efficiency. The company also builds Teraflux Bitcoin mining products, including air-, hydro-, and immersion-cooled miners, ASICs, modular containers, miner firmware, fleet-management software, and enterprise customer support.
Skills
Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
You drive physical implementation and sign-off of critical blocks for AI and high-performance computing silicon. You own designs from RTL to GDSII, optimize floorplans, placement, clocking, routing, timing, power, and area, resolve design-closure issues, develop automation flows, lead sign-off activities, and mentor engineers through silicon delivery.
Requirements
- 8+ years of hands-on experience in physical design implementation and sign-off
- Experience delivering high-performance blocks from RTL to GDSII in advanced technology nodes
- Experience closing CPU, GPU, VPU, memory controller, DDR, NoC, AI accelerator, or compute-intensive blocks
- Expertise in synthesis, floorplanning, placement, CTS, routing, extraction, timing closure, and physical sign-off
- Expertise in static timing analysis, timing constraints, clocking methodologies, multi-corner multi-mode closure, and timing ECO implementation
- Experience with Synopsys Fusion Compiler, Cadence Innovus, PrimeTime, StarRC, Calibre, or Apache RedHawk
- Experience with advanced process technologies, preferably sub-5nm nodes
- Understanding of power planning, IR drop, electromigration, signal integrity, congestion analysis, and physical design quality checks
- Scripting skills in Tcl, Perl, or Python
- Experience with low-power implementation, UPF, DFT, package-aware implementation, or hierarchical design
Responsibilities
- Own critical design blocks from RTL to GDSII
- Implement and optimize floorplans, power plans, placement, clock tree synthesis, routing, extraction, and sign-off closure
- Drive timing convergence across multiple modes and corners
- Evaluate microarchitecture tradeoffs with RTL and architecture teams
- Develop physical design methodologies, implementation recipes, and automation flows
- Perform synthesis, placement optimization, CTS, routing, timing ECOs, physical ECOs, extraction, and sign-off
- Resolve timing, congestion, clocking, signal integrity, power integrity, and physical verification issues
- Perform DRC, LVS, ERC, antenna, density, metal fill, and layout quality checks
- Drive EM/IR analysis and power delivery sign-off
- Create scripts to automate physical design tasks
- Collaborate with RTL, DFT, STA, verification, CAD, packaging, and product engineering teams
- Provide technical leadership and mentor engineers
Benefits
- Performance-based incentives
- Equity participation
- Medical coverage
- Dental coverage
- Vision coverage
- Paid time off
- Flexible work arrangements
- Professional development opportunities
