Lead RTL Design Engineer
47 minutes agoLeadSalary: 175K - 275KSunnyvale, USAOnsiteFull TimeEngineeringJobs by Cerebras Systems, Inc.
Cerebras Systems, Inc.Visit Cerebras Systems, Inc. website
Cerebras builds wafer-scale AI computing systems and a cloud inference platform for training, fine-tuning, and serving AI models.
Sunnyvale, California, United States
About Cerebras Systems, Inc.
Cerebras Systems is an AI-infrastructure company founded in 2015. It sells rack-scale wafer-scale computing systems and provides cloud-based, API-accessible AI inference alongside on-premises deployments.
Skills
Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
You will drive chip design from functional specification and microarchitecture through RTL development and synthesis. You will manage an external ASIC vendor, partner with physical design, verification, DFT, software, and systems teams, and debug silicon-level functional, timing, and power issues during bring-up.
Requirements
- Master’s degree in Computer Science, Electrical Engineering, or equivalent
- Ability to work in a hybrid work environment
- 8–15 years of experience delivering complex, high-performance RTL designs
- Experience with front-end chip integration and third-party IP integration
- Experience in networking, high-performance computing, machine learning, or related fields
- Track record of multiple silicon successes
- Experience collaborating with and managing external vendors
- Experience designing or integrating high-speed I/O
- Knowledge of TCP/IP, RDMA, Ethernet, PCIe, CPU interfaces, and Serdes
- Working knowledge of Python and TCL
Responsibilities
- Drive functional specification, microarchitecture, RTL development, and synthesis
- Manage the external ASIC vendor through the product-development cycle
- Partner with physical design to achieve design closure and PPA goals
- Work with verification and DFT teams to achieve functional and test coverage
- Partner with software and systems teams to optimize product performance and features
- Debug silicon-level functional, timing, and power issues during bring-up