Hardware Design Verification Engineer
FuriosaAI is a South Korean AI semiconductor company building energy-efficient inference accelerators, servers, and software for enterprise and cloud AI deployments.
Funding history
Investors
About FuriosaAI
FuriosaAI develops the RNGD AI inference accelerator and NXT RNGD Server, alongside a software toolchain for compiling, optimizing, and deploying LLM and agentic-AI workloads.
Skills
Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
You will define and implement verification plans for blocks, IP, subsystems, and SoCs. You will build test benches, develop functional tests, drive verification closure through coverage metrics, debug design failures with the Design team, and collaborate with design, model, emulation, and silicon-validation teams.
Requirements
- 3+ years of block, IP, subsystem, or SoC verification using SystemVerilog and UVM methodologies
- EDA tools
- Python, TCL, Perl, or Shell scripting
- Design Verification infrastructure
- Full verification-cycle execution
Responsibilities
- Define and implement verification plans
- Build verification test benches
- Develop functional tests
- Drive design verification to closure using coverage metrics
- Debug, root-cause, and resolve functional design failures
- Collaborate with design, model, emulation, and silicon-validation teams