Director of ASIC Design

Positron AI builds hardware and software for energy-efficient generative-AI and Transformer-model inference.

Reno, Nevada, United States
About Positron AI

Reno-based AI-infrastructure company whose currently shipping Atlas inference server is complemented by planned Asimov custom accelerator silicon and Titan inference systems.

View jobs by Positron AI

Skills

Candidate Availability

Required and preferred rules are kept separate and reflect the wording in the original posting.

About the Role

You will lead design, development, verification, and execution for high-performance AI inference chips. You will define ASIC architecture, microarchitecture, and roadmaps; optimize power, performance, area, and memory subsystems; and oversee the full chip-development lifecycle. You will drive tapeout and bring-up, work on hardware-software co-design, manage foundry and vendor relationships, and recruit, mentor, and develop ASIC engineers.

Requirements

  • Degree in Electrical Engineering, Computer Engineering, or a related field
  • 12+ years of ASIC development experience, including at least 5 years in a leadership role
  • Track record of delivering multiple ASIC/COT projects from concept to mass production
  • Knowledge of digital design, verification, physical design, and manufacturing processes
  • Experience with AI accelerators, high-performance computing, or data-center chip designs
  • Knowledge of Verilog/SystemVerilog, synthesis, and timing closure
  • Expertise in low-power design and power optimization for high-performance chips
  • Expertise in memory subsystem optimization
  • Familiarity with Cadence, Synopsys, and Mentor Graphics EDA tools
  • Leadership, communication, and cross-functional collaboration skills
  • Based in the Austin, Texas metropolitan area
  • Authorization to work in the U.S.

Responsibilities

  • Lead ASIC design, verification, and implementation for AI inference hardware
  • Define ASIC architecture, microarchitecture, and roadmap
  • Optimize power, performance, area, and memory subsystem trade-offs
  • Oversee RTL design, physical design, verification, and validation across the chip-development lifecycle
  • Drive COT tapeout, bring-up, first-silicon validation, and production ramp-up
  • Collaborate with software and prototyping teams on hardware-software co-design
  • Manage relationships with foundries, IP vendors, and EDA tool providers
  • Recruit, mentor, and develop the ASIC team

Benefits

  • Equity
  • Company-paid medical, dental, and vision insurance for employees and dependents
  • Company-paid life and disability coverage
  • Supplemental hospital, critical illness, and accident coverage
  • Unlimited paid time off
  • 13 paid company holidays
  • Company-provided computer and home office setup
  • 401(k) with company matching from day one
  • H-1B visa transfer facilitation for eligible candidates