Custom Characterization Engineer (Staff)

Velaura AI develops ultra-low-power silicon and software technologies for AI compute infrastructure. Its solutions serve hyperscale data centers and Physical AI applications such as robotics, autonomous systems, drones, and edge devices.

Series C0 current maintainers0 active leadsTeam intelligence

Maintainer signals as of 8/23/2026

Santa Clara, USA
About Velaura AI, Inc.

Velaura AI is an AI compute infrastructure company developing ultra-low-power silicon and software technologies. Its Titan Core™ platform uses proprietary digital chip IP, low-voltage libraries, EDA flows, and design methodologies to improve performance per watt in AI accelerators while maintaining performance, yield, and reliability. The company also applies this technology to Physical AI systems, including industrial robots, autonomous machines, drones, humanoids, and edge devices. Velaura engages hyperscalers, XPU companies, and developers of next-generation AI infrastructure and Physical AI solutions.

View jobs by Velaura AI, Inc.

Skills

Candidate Availability

Required and preferred rules are kept separate and reflect the wording in the original posting.

About the Role

Develop and deliver standard-cell timing, power, and noise models for advanced semiconductor technologies. Drive characterization methodologies, automation, model validation, statistical verification, and robust library releases in collaboration with circuit design and engineering teams.

Requirements

  • 5+ years of experience characterizing standard-cell libraries for advanced process technologies.
  • Hands-on experience with deep submicron, FinFET, and GAA technologies.
  • Expertise in Liberty model generation and validation, including NLDM, CCS, ECSM, and LVF.
  • Experience developing characterization automation, regression, and quality-assurance frameworks.
  • Proficiency with HSPICE, PrimeSim XA, or Spectre.
  • Experience with statistical characterization and Monte Carlo simulation.
  • Exposure to parasitic extraction using StarRC or Quantus.
  • Working knowledge of transistor-level standard-cell circuit design and optimization.
  • Master's degree in Electrical Engineering, Electronics Engineering, or a related field preferred.
  • Programming and automation experience using Python, Tcl, or Perl preferred.

Responsibilities

  • Own characterization and quality assurance of standard-cell libraries across advanced technology nodes.
  • Develop and optimize standard-cell characterization methodologies for timing, power, and noise models.
  • Generate and validate Liberty views including NLDM, CCS, ECSM, and LVF models.
  • Develop and maintain characterization, simulation, regression, and automation flows.
  • Perform statistical verification and Monte Carlo analysis.
  • Collaborate with circuit and layout teams to optimize standard cells.
  • Partner with engineering teams to deliver high-quality library releases.

Benefits

  • Performance-based incentives
  • Equity participation
  • Medical coverage
  • Dental coverage
  • Vision coverage
  • Paid time off
  • Flexible work arrangements
  • Professional development opportunities