Senior Staff Physical Design Engineer

Skills

About the Role

You will implement digital blocks from synthesis through physical verification in advanced technology nodes. You will drive timing closure, power analysis, floorplanning, clock distribution, DRC and LVS cleanup, ECO implementation, tool issue resolution, and automation of physical-design flows.

Requirements

• Bachelor’s degree in Electrical Engineering or Computer Engineering
• 12+ years of industry experience as a Physical Design Engineer
• Experience completing block-level or top-level physical design for large ASICs or mixed-signal chips that taped out
• Knowledge of timing closure and LVS/DRC closure
• Experience with TCL and Python or other scripting languages
• Teamwork and cross-functional collaboration skills

Responsibilities

• Implement digital blocks from synthesis through physical verification using industry-standard tools and flows
• Drive full-chip STA signoff, review constraints, debug timing reports, and implement ECOs
• Drive power analysis and optimization while balancing area and performance trade-offs
• Drive full-chip floorplanning, IO placement, and clock distribution
• Customize clock implementation for functional and test clocks
• Debug and clean up DRC and LVS issues
• Implement functional and timing ECOs
• Work with EDA companies to resolve tool issues
• Write TCL, Python, or Shell scripts to automate or customize flows

Benefits

• Comprehensive health care plan including medical, dental, and vision coverage
• Retirement savings matching program
• Life insurance including basic, voluntary, and AD&D coverage
• Vacation, sick time, and public holidays
• Paid family leave
• Short-term and long-term disability coverage
• Training and development
• Commuter benefits
• Flexible hybrid workplace model
• Equity grants for eligible full-time employees