Senior/Staff Design Verification Engineer (SOC)
Bitdeer is a technology company providing Bitcoin mining solutions.
Maintainer signals as of 9/25/2026
Funding history
Investors
Projects
About Bitdeer
Bitdeer provides full-spectrum Bitcoin mining and high-performance computing solutions, including SEALMINER mining equipment, Minerbase cooling containers, cloud mining, co-mining, mining management applications, mining rights marketplaces, and large-scale data center operations. The company also offers AI cloud infrastructure with GPU computing, model training and deployment capabilities, and turnkey AI data center solutions for enterprise customers and developers. Bitdeer is headquartered in Singapore and operates globally.
Skills
Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
Join Bitdeer's IC development team to verify complex digital designs through comprehensive verification environments, systematic test plans, simulation, emulation, debugging, and coverage-driven verification. The role uses UVM, SystemVerilog, Verilog, SVA, co-simulation, system emulation, and advanced platforms including Palladium, HAPS, and Zebu.
Requirements
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Strong understanding of digital logic design and RTL development using Verilog or other HDLs.
- Proficiency with AMBA protocols including AXI, AHB, and APB.
- Hands-on RTL simulation, debugging, and waveform analysis experience with EDA tools.
- Proficiency with SystemVerilog and UVM.
- Familiarity with Linux or Unix and automation scripting using Bash, C Shell, Perl, or Python.
- Experience with Git or SVN.
- Strong analytical, debugging, communication, documentation, and teamwork skills.
- Experience with NoC, PCIe, or DRAM memory controllers is preferred.
- Experience using AI agents for verification productivity is preferred.
- Familiarity with RISC-V or CPU verification is preferred.
- C/C++ experience for testbench development or verification utilities is preferred.
- Exposure to coverage-driven verification and regression automation is preferred.
Responsibilities
- Apply UVM, SystemVerilog, Verilog, and SVA in verification tasks.
- Develop verification methodologies using UVM, C/C++, co-simulation, system emulation, and mixed-mode simulation/emulation.
- Contribute to projects using Palladium, HAPS, and Zebu platforms.
- Collaborate with design and verification engineers to define and refine verification test plans.
- Implement test cases, stimulus, and test patterns for DUT functionality and corner cases.
- Execute simulations and analyze and debug RTL issues using waveform tools.
- Maintain regression test suites and validate design changes.
- Monitor and improve functional and code coverage metrics.
- Document test cases, verification results, and coverage reports.
- Develop automation scripts, reusable verification components, and Verification IP.
Benefits
- Attractive welfare benefits and developmental opportunities such as training and mentoring.
- Inclusive environment with opportunities to contribute directly to the digital asset industry.
- Fast-growing company with networking, autonomy, accountability, and learning opportunities.
