Senior Engineer CAD Pre-Silicon Front End
Velaura AI develops ultra-low-power silicon and software technologies for AI compute infrastructure.
Maintainer signals as of 9/2/2026
Funding history
About Velaura AI, Inc.
Velaura AI is an AI compute infrastructure company developing ultra-low-power silicon and software technologies. Its Titan Core™ platform uses proprietary digital chip IP, low-voltage libraries, EDA flows, and design methodologies to improve performance per watt in AI accelerators while maintaining performance, yield, and reliability. The company also applies this technology to Physical AI systems, including industrial robots, autonomous machines, drones, humanoids, and edge devices. Velaura engages hyperscalers, XPU companies, and developers of next-generation AI infrastructure and Physical AI solutions.
Skills
Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
You will own RTL, register-generation, design-verification, emulation, and FPGA-prototyping flows. You will build AI-assisted tooling, maintain reliable engineering workflows, improve productivity, and partner on DFT and physical-design handoff readiness.
Requirements
- Eight or more years in design verification, design, or CAD engineering
- SystemVerilog and RTL fluency
- Experience building and running simulation and regression flows
- Python skills
- Knowledge of Synopsys, Cadence, or Siemens EDA tools
- Knowledge of Linux administration and distributed compute systems such as LSF or Slurm
- Familiarity with databases and dashboarding tools such as Grafana
- Experience supporting live engineering flows
Responsibilities
- Own RTL design flows including build, lint, CDC, and formal checks
- Own register generation and generator-driven interface and integration flows
- Own design-verification flows including testbench builds, regressions, and coverage collection
- Own emulation and FPGA-prototyping builds and bring-up
- Build and deploy AI-assisted tooling for design and verification workflows
- Maintain tools, manage versions, and resolve maintenance requests
- Measure and improve design and verification productivity
- Partner on DFT and physical-design handoff readiness
Benefits
- Equity compensation
- Medical coverage
- Dental coverage
- Vision coverage
- Paid time off
- Flexible work arrangements