Senior Design Verification Engineer
FuriosaAI is a South Korean AI semiconductor company building energy-efficient inference accelerators, servers, and software for enterprise and cloud AI deployments.
Funding history
Investors
About FuriosaAI
FuriosaAI develops the RNGD AI inference accelerator and NXT RNGD Server, alongside a software toolchain for compiling, optimizing, and deploying LLM and agentic-AI workloads.
Skills
Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
You will define and implement block- and system-level verification strategies. You will write and review test plans, develop test harnesses and sequences, and drive verification closure against coverage metrics. You will debug functional failures with design partners and coordinate verification work across relevant functions.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Science, or a related technical field
- 5+ years of block- and system-level verification experience using SystemVerilog and UVM
- Experience with EDA tools
- Proficiency in Python, Perl, and shell scripting for verification tools and flows
- Experience architecting and deploying design verification infrastructure through the complete verification cycle
- Experience developing UVM-based verification environments
- Experience developing Python-based verification environments such as cocotb
- Experience verifying high-speed interfaces such as PCIe, UCIe, UALink, and Ethernet
- Experience verifying ARM- or RISC-V-based subsystems or SoCs
- Python programming skills
- Written and verbal communication skills
Responsibilities
- Define, plan, and implement block- and system-level verification strategies
- Write and review test plans
- Develop test harnesses and test sequences
- Drive verification closure using test-plan, functional-coverage, and code-coverage metrics
- Debug, root-cause, and resolve functional design failures
- Collaborate with Design, Model, Emulation, and Silicon Validation functions to ensure design quality