RTL Power Engineer

Velaura AI develops ultra-low-power silicon and software technologies for AI compute infrastructure. Its solutions serve hyperscale data centers and Physical AI applications such as robotics, autonomous systems, drones, and edge devices.

Series C0 current maintainers0 active leadsTeam intelligence

Maintainer signals as of 8/23/2026

Santa Clara, USA
About Velaura AI, Inc.

Velaura AI is an AI compute infrastructure company developing ultra-low-power silicon and software technologies. Its Titan Core™ platform uses proprietary digital chip IP, low-voltage libraries, EDA flows, and design methodologies to improve performance per watt in AI accelerators while maintaining performance, yield, and reliability. The company also applies this technology to Physical AI systems, including industrial robots, autonomous machines, drones, humanoids, and edge devices. Velaura engages hyperscalers, XPU companies, and developers of next-generation AI infrastructure and Physical AI solutions.

View jobs by Velaura AI, Inc.

Skills

Candidate Availability

Required and preferred rules are kept separate and reflect the wording in the original posting.

About the Role

You will own SoC power management across all design levels. You will design power meters, activity monitors, throttlers, thermal control loops, power and activity limit controls, clock and reset systems, and low-power state management. You will correlate power estimates across RTL, emulation, and silicon, build field telemetry, and define interfaces with firmware and software controls.

Requirements

  • Understand the electrical engineering and physics of average power peak current thermal behavior and voltage droop
  • Have experience designing power management hardware and thermal or current control loops
  • Understand di/dt IR drop and power delivery network behavior
  • Have experience with clock and reset architecture clock gating and PLL management
  • Have working knowledge of Verilog or SystemVerilog and modern RTL methodology
  • Have experience with power estimation and analysis from RTL through gate level
  • Have strong debugging and problem-solving skills across hardware and software boundaries
  • Hold a BS or higher in Electrical Engineering Computer Engineering or a related field
  • Experience with DVFS adaptive voltage scaling adaptive clocking UPF low-power design thermal modeling firmware PMIC interfaces or power analysis tools is preferred

Responsibilities

  • Design on-chip power management hardware including digital power meters activity monitors and throttlers
  • Design hardware and software control loops around temperature sensors
  • Design controls for activity average-power and instantaneous di/dt limits
  • Address voltage droop power delivery and adaptive clocking behavior
  • Own clock and reset architecture including clock gating PLL management and reset sequencing
  • Define and implement DVFS power domains retention and low-power flows
  • Correlate power estimates across RTL emulation and silicon and build telemetry
  • Define interfaces policies and telemetry with firmware and software teams

Benefits

  • Performance-based incentives
  • Equity participation
  • Medical coverage
  • Dental coverage
  • Vision coverage
  • Paid time off
  • Flexible work arrangements
RTL Power Engineer at Velaura AI, Inc. | JobStash