RTL Lead – Physical AI Compute
Velaura AI develops ultra-low-power compute technology for cloud, edge, and physical AI applications. It also offers Teraflux Bitcoin mining hardware, fleet-management software, and related support for mining operators.
Funding history
Projects
About Velaura AI
Velaura AI is a semiconductor and technology company that provides patented ultra-low-power silicon design technology, IP, toolflows, and custom chiplet solutions for AI compute platforms. Its customers include hyperscaler and XPU companies seeking reduced power consumption and higher compute efficiency. The company also builds Teraflux Bitcoin mining products, including air-, hydro-, and immersion-cooled miners, ASICs, modular containers, miner firmware, fleet-management software, and enterprise customer support.
Skills
Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
You will lead RTL development for key portions of a Physical AI SoC. You will translate system requirements into microarchitectures, drive hardware/software co-design, make performance and power decisions, review RTL, establish engineering methodologies, and mentor RTL engineers.
Requirements
- Strong RTL design experience in complex SoCs or related systems
- Deep understanding of digital design fundamentals and microarchitecture
- Experience with Verilog and SystemVerilog
- Familiarity with memory systems, interconnect fabrics, cache hierarchies, and system-level data movement
- Experience balancing performance, power, area, and design complexity
- Ability to drive technical projects from concept through silicon bring-up
- Experience with hardware/software co-design and system-level performance optimization
Responsibilities
- Lead RTL development across key SoC components
- Translate system requirements into robust microarchitectures
- Drive hardware/software co-design across AI workloads, memory systems, runtime software, and system architecture
- Define programming models, execution flows, memory hierarchies, and performance-critical interfaces
- Drive design decisions across compute engines, memory subsystems, interconnect, control logic, and system infrastructure
- Conduct architecture and RTL reviews
- Establish engineering processes and design methodologies
- Mentor and develop RTL engineers
Benefits
- Performance-based incentives
- Equity participation
- Medical coverage
- Dental coverage
- Vision coverage
- Paid time off
- Flexible work arrangements