DFT Engineering Leader
Bitdeer is a NASDAQ-listed company specializing in Bitcoin mining, AI cloud services, and data center operations. They provide comprehensive mining solutions, AI development services, and operate seven global data centers with a significant portion of their energy being carbon-free.
About Bitdeer Technologies Group
Bitdeer is a high-performance computing platform that specializes in Bitcoin mining and AI cloud services. The company constructs and operates numerous cutting-edge data centers globally, including one of North America's largest, with a focus on using clean energy. Their product offerings include SEALMINER, which are high-performance and efficient chips; Cloud Mining services that allow users to participate in mining remotely; and Minerbase, a mobile intelligent cooling system. In addition to their crypto-focused services, Bitdeer is expanding into the AI sector by providing high-performance computing for AI/ML acceleration using NVIDIA DGX H100s, offering turnkey AI datacenter solutions, and developing an end-to-end AI application sharing ecosystem. They cater to both individual and institutional clients with a range of services like after-sales support, a hash rate market, and data center support.
Skills
About the Role
You will lead DFT engineering efforts, working on advanced test and design-for-test methodologies for cutting-edge chip designs. You will implement and optimize boundary scan, MBIST, test logic insertion, and JTAG solutions, and develop and validate scan ATPG and compression methodologies. You will conduct DFT and post-gate simulation processes to ensure design robustness, generate and apply DFT constraints for efficient testing, and deliver effective test patterns while collaborating with the test team on ATE debugging. You will use EDA tools like Tessent to enhance test processes and efficiency, and provide technical mentorship and guidance to junior engineers.
Requirements
- Bachelor/Master/PhD degree in Electrical Engineering or Computer Engineering
- At least 8 years of relevant experience
- Proficiency in synthesis tools such as Genus or Design Compiler
- Experience working closely with designers to create test plans and strategies
- Proven ability to collaborate with implementation teams for DFT insertion and resolve DFT-related timing or congestion challenges
- Highly driven and detail-oriented
Responsibilities
- Implement and optimize boundary scan, MBIST, test logic insertion, and JTAG solutions
- Develop and validate scan ATPG and compression methodologies
- Conduct DFT and post-gate simulation processes to ensure design robustness
- Generate and apply DFT constraints for efficient testing
- Deliver effective test patterns and collaborate with the test team for ATE debugging
- Utilize EDA tools like Tessent to enhance test processes and efficiency
- Provide technical mentorship and guidance to junior engineers
Benefits
- Attractive welfare benefits and developmental opportunities such as training and mentoring