Design Verification Engineer Interface IP
EtchedVisit Etched website
Etched is an AI-hardware company building rack-scale frontier inference clusters.
San Jose, United States
Funding history
About Etched
Etched co-designs chips, racks, software, and manufacturing systems for efficient inference of frontier AI models, targeting throughput, latency, cost, and power efficiency across prefill and decode workloads.
Skills
Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
You will own verification for interface IP subsystems, coordinate vendor-IP configuration with the internal IP team, build UVM/SystemVerilog verification environments, collaborate on integration, and define coverage metrics to achieve verification closure and sign-off.
Requirements
- Design verification experience
- SystemVerilog
- UVM
- Testbench development
- PCIe
- Ethernet
- AXI
- AMBA
- ARM
- ARC
- IP interface verification
Responsibilities
- Own verification of interface IP subsystems
- Manage vendor IP configurations and coordination with the internal IP team
- Develop and maintain UVM/SystemVerilog verification environments
- Collaborate with integration and SoC DV teams on external-IP validation
- Drive coverage closure and verification sign-off
Benefits
- Medical, dental, and vision coverage
- $500 per month credit for waiving medical benefits
- Wellness benefits
- Daily lunch and dinner
- Unlimited compute budget subject to ROI justification