Accelerator Compiler and Tool Chain Lead
Velaura AI develops ultra-low-power silicon and software technologies for AI compute infrastructure. Its solutions serve hyperscale data centers and Physical AI applications such as robotics, autonomous systems, drones, and edge devices.
Maintainer signals as of 8/23/2026
Funding history
About Velaura AI, Inc.
Velaura AI is an AI compute infrastructure company developing ultra-low-power silicon and software technologies. Its Titan Core™ platform uses proprietary digital chip IP, low-voltage libraries, EDA flows, and design methodologies to improve performance per watt in AI accelerators while maintaining performance, yield, and reliability. The company also applies this technology to Physical AI systems, including industrial robots, autonomous machines, drones, humanoids, and edge devices. Velaura engages hyperscalers, XPU companies, and developers of next-generation AI infrastructure and Physical AI solutions.
Skills
Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
Own the compiler and model-lowering stack for an AI accelerator, covering model ingestion, graph lowering, compiler IR, optimization passes, quantization integration, code generation, diagnostics, verification, regression strategy, and team leadership.
Requirements
- Deep experience with compiler development, ML graph compilers, or accelerator code generation
- Strong understanding of ML model formats, graph IRs, operator lowering, tensor layouts, quantization, and runtime/compiler interfaces
- Strong C++ and Python programming skills
- Experience with MLIR, LLVM, TVM, XLA, IREE, Glow, TensorRT-like systems, OpenVINO-like systems, or equivalent
- Understanding of correctness risks in compiler optimizations, graph rewrites, mixed precision, operator fusion, and hardware-specific lowering
- Ability to collaborate with hardware, firmware, runtime, model-integration, and SQA engineers
- Experience leading technical teams or major architecture areas
Responsibilities
- Lead architecture and development of the AI accelerator compiler stack
- Own model ingestion and graph lowering from ML frameworks and exchange formats
- Define operator coverage, lowering rules, graph transformations, fusion, partitioning, and fallback behavior
- Develop compiler optimization passes for tensor layout, tiling, memory movement, mixed precision, operator fusion, and hardware scheduling
- Define executable artifact formats, metadata, memory planning requirements, profiling hooks, and runtime constraints
- Integrate quantization compilation
- Build compiler diagnostics for unsupported operators, shape constraints, graph rewrites, quantization issues, and performance bottlenecks
- Establish compiler verification and regression strategies
- Hire, mentor, and lead compiler and ML systems engineers
Benefits
- Performance-based incentives
- Equity participation
- Medical coverage
- Dental coverage
- Vision coverage
- Paid time off
- Flexible work arrangements