Senior/Staff Design Verification Engineer (SOC)

Skills

About the Role

You'll join the IC development team to help ensure the functional correctness and robustness of complex digital designs. You will work closely with design and verification teams to develop comprehensive verification environments, execute test plans, and contribute to high-quality silicon through systematic and coverage-driven verification. You will apply UVM, SystemVerilog, Verilog, and SVA in verification tasks, and develop verification methodologies including co-simulation, system emulation, and mixed-mode simulation/emulation. You will also contribute to projects requiring advanced verification tools such as Palladium, HAPS, and Zebu platforms.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (or currently pursuing the degree for entry-level roles)
• Solid understanding of digital logic design and RTL development using Verilog or other Hardware Description Languages (HDL)
• Proficiency with AMBA bus protocols (AXI, AHB, APB)
• Hands-on experience with RTL simulation, debugging, and waveform analysis using industry-standard EDA tools (e.g., Synopsys, Cadence, or Siemens EDA / Mentor)
• Proficiency with SystemVerilog and modern verification methodologies such as UVM
• Familiarity with Linux/Unix environments and scripting for automation (e.g., Bash, C Shell, Perl, or Python)
• Experience using version control systems such as Git or SVN in a collaborative development environment
• Good analytical and debugging skills, with the ability to identify and resolve RTL and functional issues
• Strong communication skills in English, both written and verbal, with the ability to document verification results clearly
• Self-motivated, detail-oriented, and able to work effectively both independently and within a team environment
• Experience with one or more of these technologies: NoC (network on chip), PCIe (Gen-4 onwards), DRAM memory controller
• Experience with using AI Agent for verification productivity
• Familiarity with RISC-V processor architecture or CPU verification concepts
• Experience with C/C++ programming for testbench development or verification utilities
• Exposure to coverage-driven verification and regression automation workflows

Responsibilities

• Apply UVM, SystemVerilog, Verilog, and SVA languages in verification tasks
• Develop and implement verification methodologies including UVM, C/C++, co-simulation, system emulation, and mixed-mode simulation/emulation
• Contribute to projects requiring advanced verification tools such as Palladium, HAPS, and Zebu platforms
• Collaborate effectively within a team to ensure high-quality deliverables
• Understand the Design Under Test including its architecture, interfaces, and functional requirements
• Collaborate with verification and design engineers to define, review, and refine verification test plans based on design specifications
• Implement test cases, stimulus, and test patterns to validate DUT functionality and corner cases
• Execute simulations and analyze/debug RTL issues using waveform analysis and debugging tools
• Run and maintain regression test suites to validate design changes and ensure design stability across development cycles
• Monitor and improve functional and code coverage metrics, contributing to coverage-driven verification and verification closure
• Document test cases, verification results, and coverage reports to support verification sign-off
• Contribute to the development and maintenance of automation scripts, reusable verification components, and Verification IP (VIP) to enhance team productivity

Benefits

• Attractive welfare benefits and developmental opportunities such as training and mentoring