Principal Packaging Engineer
Auradine is pioneering innovative solutions for world-leading blockchain and cutting-edge AI applications by developing breakthrough technologies like energy-efficient silicon, robust infrastructure, and state-of-the-art software. The company provides Web infrastructure solutions, including their Teraflux™ product line and associated developer tools like the Miner API.
Projects
About Auradine
Auradine is pioneering innovative solutions for world-leading blockchain and cutting-edge AI applications by developing breakthrough technologies like energy-efficient silicon, robust infrastructure, and state-of-the-art software. Auradine focuses on breakthrough scalability and sustainability for the future of internet infrastructure, enabled by revolutionary blockchain and AI technologies. The company develops complete solutions, including software and silicon systems, and offers its customers both system-level and cloud solutions. Auradine offers a range of products under the Teraflux™ brand, including the AH3880, AT2880, AI3680, AT1500, and AI2500 models, as detailed in their datasheets. They also provide a Teraflux™ Miner API Reference for developers.
Skills
About the Role
You will own package architecture from concept through production for Velaura SoCs. You'll partner with architecture and silicon teams to co-optimize package, die, board, and system design for performance, power, cost, and manufacturability. You'll drive package technology selection and lead package design efforts while collaborating with OSAT and substrate vendors to bring products to production. You'll also help shape Velaura's long-term packaging roadmap as future products evolve.
Requirements
- Deep experience developing advanced semiconductor packages for high-performance SoCs
- Strong understanding of package architecture, substrate technologies, bumping, assembly flows, and manufacturing
- Experience co-optimizing package design with silicon, board, SI/PI, thermal, and mechanical teams
- Hands-on experience with signal integrity, power integrity, thermal, and reliability considerations in advanced packages
- Ability to balance technical excellence with cost, yield, manufacturability, and schedule
- Excellent communication skills and a collaborative, first-principles engineering mindset
- Advanced packaging technologies including chiplets, 2.5D integration, silicon bridges, or heterogeneous integration (preferred)
- HBM integration and high-bandwidth memory package architecture (preferred)
- Advanced process nodes (N3, N2, or beyond) (preferred)
- Experience working with leading foundries, OSATs, and substrate vendors (preferred)
- Experience in an early-stage semiconductor company (preferred)
Responsibilities
- Own package architecture from concept through production for Velaura SoCs
- Partner with architecture and silicon teams to co-optimize package, die, board, and system design for performance, power, cost, and manufacturability
- Drive package technology selection, including flip-chip, advanced substrates, fan-out, and future multi-die integration approaches
- Lead package design, bump planning, substrate definition, escape routing, and assembly interactions with OSAT and substrate vendors
- Own package-level signal integrity and power integrity planning for high-speed interfaces including LPDDR, PCIe, Ethernet, and other high-speed I/O
- Collaborate on thermal architecture, mechanical integration, reliability, DFM, and qualification
- Work with foundry, assembly, substrate, and test partners to successfully deliver products to production
- Help define Velaura's long-term packaging roadmap as future products evolve
Benefits
- Equity participation
- Medical, dental, and vision coverage
- Paid time off
- Flexible work arrangements
- Professional development opportunities