DDR & HBM Validation Engineer
Graphcore is a Bristol-based AI chipmaker (IPU accelerators), a SoftBank subsidiary and a Molten Ventures portfolio company.
Maintainer signals as of 8/23/2026
About Graphcore
Graphcore (graphcore.ai) is a British semiconductor company building Intelligence Processing Units (IPUs) for AI workloads. Founded in Bristol in 2016, it was acquired by SoftBank in 2024. It is a portfolio company of Molten Ventures.
Skills
Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
This role is responsible for bringing up, validating, characterizing and debugging advanced DDR and HBM memory subsystems used in next-generation AI compute platforms. The engineer will work with silicon design, firmware, characterization, platform and systems teams to ensure robust functionality, performance and reliability from first silicon through production readiness.
Requirements
- Strong experience validating DDR, LPDDR, HBM or related DRAM technologies
- Deep understanding of DRAM architecture, memory subsystems and memory controllers
- Experience with firmware, BIOS and Embedded C development
- Strong programming skills in C and Python
- Hands-on experience with oscilloscopes and laboratory measurement instrumentation
- Experience with GPIO, SPI, I2C and UART/serial interfaces
- Experience with functional testing, voltage, frequency and timing analysis
- Strong embedded systems and microcontroller knowledge
- Hands-on board bring-up and hardware validation experience
- Experience debugging complex hardware, firmware and system issues
- Experience with silicon characterization and validation-result analysis
- Strong analytical, diagnostic and problem-solving skills
- Excellent communication and multidisciplinary collaboration skills
- Experience with memory IP bring-up, firmware or validation software
- Knowledge of DDR/HBM PHY behavior, training algorithms and calibration
- Knowledge of memory performance analysis and workload characterization
- Experience with memory margining, stress testing and reliability validation
- Familiarity with JTAG, trace infrastructure and low-level debug tools
- Experience with high-performance compute, AI accelerator or data center systems
- Understanding of signal integrity and power integrity in high-speed memory systems
- Experience developing validation automation and regression environments
- Experience supporting first-silicon bring-up and production readiness
Responsibilities
- Execute validation and bring-up activities for DDR and HBM memory subsystems
- Verify memory bring-up software, firmware and scripts against project requirements
- Debug firmware, hardware and system-level issues and contribute to root-cause analysis
- Analyze system logs, validation data and characterization results
- Perform PHY characterization and analog-level analysis during stress testing
- Develop and execute functional, stress, performance and corner-case validation tests
- Perform signal integrity, voltage, frequency and timing measurements
- Characterize memory bandwidth, latency, training behavior and subsystem stability
- Develop Python-based automation, test infrastructure and reporting tools
- Collaborate with architecture, RTL, firmware and platform teams
- Support memory subsystem debug across silicon, firmware, board and system domains
- Support validation methodologies, debug procedures and reporting frameworks
- Improve validation infrastructure and engineering processes
- Support silicon characterization, production readiness and qualification activities
- Document validation results and communicate findings